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Google's eighth-generation TPU announcement in April 2026 split the product line in two for the first time: TPU 8t for training, TPU 8i for inference. The same week, Cerebras filed a public S-1 for a

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Google's eighth-generation TPU announcement in April 2026 split the product line in two for the first time: TPU 8t for training, TPU 8i for inference. The same week, Cerebras filed a public S-1 for a twenty-three-billion-dollar IPO backed by a twenty-billion-dollar OpenAI deal. Both events point to the same inflection: the era of "one chip for everything" is ending. Training and inference workloads have diverged enough that a unified architecture is now a compromise, not a convenience.
This guide is for builders making compute decisions in that new landscape. It compares GPU clusters against custom silicon across the dimensions that actually matter: cost, flexibility, lock-in, and operational reality.
Google's move is the clearest signal. TPU 8t scales to 9,600 chips per superpod with 121 ExaFlops of training throughput, a 3D torus topology, and a claimed 2.7 times training price-performance improvement over the previous Ironwood generation. It is built for scale-out training of massive models.
TPU 8i is a different chip entirely. It uses a Boardfly topology that caps at seven hops versus sixteen in a torus, carries three times the on-chip SRAM, and includes a Collectives Acceleration Engine that reduces latency fivefold. It is optimized for low-latency serving of mixture-of-experts and reasoning models, with the KV cache kept on-chip. Google claims eighty percent inference price-performance improvement and double the performance-per-watt.
The strategic read is not the raw specs. It is that Google, with full vertical control over its stack, concluded that training and inference are different enough to warrant different silicon. If Google thinks so, builders renting compute should pay attention.
Background: Google co-designed TPU 8t/8i with DeepMind, and Gemini runs on TPUs. The split-architecture decision was not made in a vacuum. It reflects real workload divergence observed at hyperscale. Nvidia has not yet split its product line this way, though the Vera Rubin architecture is expected to address the same tension.
When a company that owns the entire stack from chip to model decides one chip is no longer enough, the rest of the market should question whether their one-size-fits-all approach still fits.
Nvidia GPUs remain the default for a reason. The ecosystem is unmatched: PyTorch, JAX, CUDA, and thousands of optimization libraries assume you are running on Nvidia silicon. If your team knows CUDA, debugging is faster. If you need a specific kernel or a community-optimized training recipe, it probably exists for GPUs first and custom silicon second.
The business model is flexible. You can rent A100s or H100s by the hour from any major cloud provider. You can buy them and depreciate them over three years. You can move workloads between providers with minimal friction because the software layer is portable. For teams that value flexibility over peak efficiency, this is the right default.
The tradeoff is cost at scale. GPU cloud pricing has crashed roughly eighty percent from peak levels, but for sustained training runs on thousands of chips, the per-FLOP economics of custom silicon still win. The question is whether your workload is large enough and consistent enough for that win to matter. A team training a 7B parameter model on a few dozen GPUs will not see the TPU advantage. A team training a frontier-scale model on thousands of chips will.
Google's TPUs offer the clearest alternative. The 2.7 times training price-performance claim and 80 percent inference improvement are significant if they hold up in independent benchmarks. Both chips use Google's Axion ARM-based CPU hosts, ditching x86 entirely. Native PyTorch support is in preview, which reduces the migration friction for teams already using standard frameworks.
Cerebras represents a different bet: wafer-scale integration. The Cerebras WSE-3 chip is a single wafer-scale engine designed for inference decode-phase latency, where Cerebras claims it outperforms Nvidia. The S-1 filing reveals $510 million in revenue for 2025, up seventy-six percent year-over-year, with a twenty-billion-dollar-plus Master Relationship Agreement with OpenAI for 750 megawatts of inference compute.
The Cerebras story has caveats. Eighty-six percent of 2025 revenue came from two UAE entities. GAAP profitability of $237.8 million is entirely a one-time $363.3 million non-cash accounting gain from restructuring a liability. The non-GAAP net loss actually widened to $75.7 million. The company is also transforming from a hardware shipper to a hyperscale cloud operator, a transition it has never executed at scale.
The AWS partnership is binding but narrow: disaggregated inference where AWS Trainium handles prefill and Cerebras handles decode, within Amazon Bedrock. It validates the architecture but does not prove Cerebras can run a cloud business.
The custom silicon bet is real, but the commercial validation is thinner than the press releases suggest. Read the S-1 footnotes before you read the headlines.
Lock-in.* GPUs run everywhere. TPUs run on Google Cloud. Cerebras runs on Cerebras Cloud or AWS Bedrock disaggregated inference. If you build on custom silicon, your portability is constrained. For startups that might need to migrate providers or sell their training infrastructure, this matters more than raw FLOPS.
Ecosystem maturity.* The debugging and profiling tooling around TPUs and Cerebras is years behind Nvidia's stack. When a training run fails at 3 AM, the speed of diagnosis often matters more than the theoretical throughput of the chip.
Pricing models.* GPU rentals are commodity-priced and transparent. TPU pricing is bundled into Google Cloud contracts with volume discounts that are hard to benchmark. Cerebras pricing is opaque and evolving as the company shifts from selling chips to selling capacity.
Apr 21, 2026
Workload fit.* TPUs excel at transformer-scale training with large batch sizes. Cerebras targets inference decode latency for long-context generation. GPUs remain the best general-purpose option for research experimentation, smaller models, and non-transformer architectures. If you are training diffusion models or reinforcement learning agents, the custom silicon advantage shrinks.
Future-proofing.* The multi-silicon future is coming, but the timeline is unclear. Nvidia's Vera Rubin architecture will arrive with significant performance improvements. Groq's LPU integration with AWS is expanding. Google's TPU roadmap now splits into training and inference tracks, which means each generation will be more specialized and less interchangeable. Betting on any single custom silicon vendor today carries the risk that their architecture becomes a dead end if the market converges on a different standard. GPUs have staying power precisely because they are the standard.
Use this rubric rather than chasing benchmark headlines.
Choose GPU clusters if:* your team is small and needs to move fast, your workloads vary across model types and scales, you value portability between cloud providers, or your budget is unpredictable and you need hourly rental flexibility.
Choose Google TPUs if:* you are training large language models at scale, you are already on Google Cloud, your workloads are stable enough to justify multi-year commitments, and you can tolerate the preview-status PyTorch support.
Choose Cerebras if:* you are serving inference at massive scale with a focus on decode-phase latency, you have a long-term partnership with OpenAI or AWS Bedrock, and you can accept the counterparty risk of a pre-IPO vendor with concentrated revenue.
Wait if:* you are not sure which workload dominates your compute budget yet. The split-architecture trend is real, but the winner in each category is not yet decided. Nvidia is not standing still : the Vera Rubin architecture and Groq LPU integration are direct competitive responses.
The specialization trend is irreversible. Training and inference have different bottlenecks: training is bound by all-reduce bandwidth and inter-chip communication; inference is bound by memory bandwidth per token and KV cache capacity. A chip optimized for both will be suboptimal at either.
For builders, the practical implication is that compute strategy is becoming workload strategy. The question is no longer "which chip is fastest?" but "which chip is fastest for my specific model, at my specific scale, with my specific latency requirements?" The answer will increasingly be: different chips for different jobs.
The transition will take years. The tooling, talent, and pricing models for multi-silicon environments are still forming. But the direction is clear. The era of GPU homogeneity is ending. The question is when to diversify, not whether.